Carl Zeiss & SEMATECH Develop Novel Design for Photomask Registration and Overlay Metrology to Enable Double-Patterning- Lithography

n a potential boost to advance lithography, engineers at SEMATECH and Carl Zeiss SMT today announced the completion of their final design for the next generation Photomask Registration and Overlay Metrology system – called PROVE™. The successful final system design release is a major milestone within the project. PROVE™ will allow for the production of more advanced photomasks with substantially improved image placement accuracy. Double patterning lithography, in particular, requires tighter image placement control for photomasks, but the new system will also enhance photomask production in general.

The new metrology system PROVE™ developed by a team of more than 40 Carl Zeiss SMT engineers and supported by SEMATECH ascertains the accuracy of mask pattern alignment, and registration for 32nm half-pitch and beyond photomasks. Double patterning is a technology for enhancing feature density by using standard 193nm wavelength technology. The newly developed metrology technology also forms part of the critical infrastructure of extreme ultraviolet (EUV) lithography. “Future lithographic scaling places a high reliance on very tight overlay control of the various device levels, and the photomask is a key component of the overlay error budget,” said Michael Lercel, SEMATECH Director of Lithography and chairman of the ITRS Litho Working Group. “This new system will get us past several previously ‘no known solution’ challenges.”

“Exploiting the core competencies of Carl Zeiss SMT and our long-term experience in 193nm lithography optics and metrology enabled us to create a revolutionary new system design which will close the technology gap for overlay metrology at 32nm and beyond. Additionally, the broad presence of ZEISS products within the mask industry will be most beneficial for our customers in providing them an increased on-site applications and service support,” said Oliver Kienzle, Member of the Board of Carl Zeiss SMT’s Semiconductor Metrology Systems Division.

“With double patterning coming on strong as an optical extension, registration tolerances are getting even smaller,” said Patricia Gabella, SEMATECH project engineer and manager of the joint project. “Working with Carl Zeiss SMT we have completed a design for quantifying image placement errors as small as 2.4 nm according to the ITRS roadmap. This is a major milestone towards making double patterning a commercially viable technology.” Gabella said the tool itself is targeted for production in 2009, with mask manufacturers being the primary customers.

http://www.zeiss.com/C1256A770030BCE0/WebViewAllE/76439906A09CCF39C12573FA0048B42E

Future of lithography still undecided

The semiconductor fabrication industry still appears to be undecided as to just what is next. 90nm seems pretty much settled, but the tools and techniques to go as far as 45nm are still very much on the drawing board. Teams from Sony have demonstrated a resolution capable of 45nm but, like Intel's well-publicized 10GHz ALUs, they're a long way from making anything real and marketable. An interesting piece at EETimes highlights the uncertainty in the industry.

Despite the fact that the industry is moving into 90 nm pilot production with existing 193 nm steppers for critical layers, vendors of alternative technologies are pushing their systems toward production.

Alternative methods, and their patent holders, see the processes beyond 90nm as their holy grail, where they can make their mark on the market. Today's extreme-ultra-violet lithography is nearing the limits of its resolution. As we have gone through optical to ultra-violet, the next logical step is x-ray lithography. Not according to JMAR Research who, as well as X-ray lithography, are researching the possible applications of Collimated Plasma Lithography (CPL) for future semiconductor fabrication.

With the big two of AMD and Intel designing x86 processors for higher and higher clock frequencies, as well as a host of embedded and mobile applications from thousands of vendors, more precise and smaller fabrication nodes are required to keep the die size down and to keep the power consumption within reasonable levels. Future fabrication techniques are designed to help designers achieve these complimentary aims which benefit both our top spec desktops and our hand held devices.

http://arstechnica.com/news.ars/post/20030301-533.html

Many options expected in the future of lithography

Maintaining the historical pace of reducing half-pitch for each technology generation requires overcoming the challenge of extending the incumbent optical projection lithography technology at 193nm while simultaneously developing alternative, next generation lithography (NGL) technologies. Not only is it necessary to invent technical solutions to challenging problems, it is critical that die costs remain economical even as the costs of design, process development, masks, resist, and exposure tools rise. Maintaining economical production costs is becoming a bigger challenge as the rising costs of developing a new generation of lithography technology must be amortized over relatively few generations of integrated circuits.

In the Difficult Challenges tables in the 2005 ITRS, stronger emphasis was placed on challenges related to immersion lithography. The 2005 chapter includes more detail describing cost of ownership, resolution enhancement techniques (RET), and design for manufacturing (DFM) with lithography-friendly design rules.

Continued emphasis was placed on challenges for implementing cost-effective post-optical lithography solutions, and more detail was added on the requirements for extreme ultraviolet (EUV), imprint, and maskless lithographies.

http://sst.pennnet.com/Articles/Article_Display.cfm?Section=ARTCL&ARTICLE_ID=247497&VERSION_NUM=2&p=5